A VHDL Methodology for FPGAs

Michael Gschwind, Valentina Salapura {mike,vanja}@vlsivie.tuwien.ac.atInstitut für Technische InformatikTechnische Universität WienTreitlstraße 3-182-2A-1040 WienAUSTRIA

Contents:
Introduction
Environment
Efficient adder implementation
State Machines
Signal Selection
Storage structures
Sequential Elements
Memory elements
Placement and Routing
Conclusion
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References
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